I honestly think this is fundamentally impossible. Factory tech and Agile just don't mix. Failing in software is cheap, but with silicon, no matter how low the tape-out costs are, every failure costs you a massive amount of physical time. Also, open-source EDA tools are currently stuck on legacy nodes. Considering the huge gap with state-of-the-art nodes, why would anyone even bother?
Software monetization works because of scale-out. (The fatal flaw of SaaS is the endless pressure to update, completely ruining the idea of 'finished' software.) But hardware? Once it's taped out, it’s a physical endpoint that needs no maintenance. How are you supposed to charge a monthly subscription for that
To add to this: the downstream customers also hate change, just as much as people hate Windows updates. They much prefer being able to buy the same chip for 10 years.
(here at Medium-Size-Fabless-Semi-Inc, I'm in the middle of revving a bunch of parts that are about 10 years old, not because we want to add new features to them but because the process node is so obsolete it's becoming difficult to fab. Yes, they're getting new features, but that's not the primary driver of business)
On the other hand, because parts are physical objects, you can charge money for them. Piracy is .. not nonexistant (ask FTDI) but not a major concern.
There are some interesting corners for rapid-rev electronics, but there's a decision tree:
- can I do this with a microcontroller?
- if not, how about an FPGA?
- ok, there really is no alternative to ASIC, is the market size enough to support that?
Why couldn't a company committed to mask fabrication and wafer fabrication, in concept, perform these steps daily, or several times daily? Multiple prototype designs could be grouped together so multiple customers can realize a new design instance in the same iteration.
With an appropriate debug core in the same wafer, designers who'd completed a tape-out could connect to their chip well enough to repeat their design-verification tests on this real hardware, remotely even (no need to physically handle the device 'til you're certain it's working.) Once satisfied, customers could promote their design to be bonded out for installation into their PCB.
"Sure thing boss, we'll add an extra USART core to this afternoon's tape out."
I sort of expected this to happen with tightly coupled customer-customizable chiplets inside a single package, instead. But it seems that packaging is also better left to Intel and AMD, I guess.
Because you are dealing with the physical world where those different designs have different requirements that can conflict. It’s like saying all software is basically the same, why don’t you just abstract it all and run it on these Raspberry Pi’s.
You can do that, but it’s going to turn out poorly.
Part of the delay is really just commercial. Fabs are optimized for utilization - throughput, not latency. A fab operator will prefer to queue up a load of work with as few gaps as possible, and your shuttle service run has to fit in one of the gaps. If you're NVIDIA and you've already booked the fab, there might not be so much delay. But not zero.
Regarding hardware, it's not entirely true that it doesn't need maintenance/development. See "stepping" https://en.wikipedia.org/wiki/Stepping_level. There are sometimes ways to tweak the masks to fix a "silicon bug".
Yes, but that still costs significant money in a way that software deployment doesn't. IME most chips get maybe one or two metal layer revisions then a rev B consolidated bugfix - and then get left alone.
(here at Medium-Size-Fabless-Semi-Inc, I'm in the middle of revving a bunch of parts that are about 10 years old, not because we want to add new features to them but because the process node is so obsolete it's becoming difficult to fab. Yes, they're getting new features, but that's not the primary driver of business)
On the other hand, because parts are physical objects, you can charge money for them. Piracy is .. not nonexistant (ask FTDI) but not a major concern.
There are some interesting corners for rapid-rev electronics, but there's a decision tree:
With an appropriate debug core in the same wafer, designers who'd completed a tape-out could connect to their chip well enough to repeat their design-verification tests on this real hardware, remotely even (no need to physically handle the device 'til you're certain it's working.) Once satisfied, customers could promote their design to be bonded out for installation into their PCB.
"Sure thing boss, we'll add an extra USART core to this afternoon's tape out."
You can do that, but it’s going to turn out poorly.
Part of the delay is really just commercial. Fabs are optimized for utilization - throughput, not latency. A fab operator will prefer to queue up a load of work with as few gaps as possible, and your shuttle service run has to fit in one of the gaps. If you're NVIDIA and you've already booked the fab, there might not be so much delay. But not zero.
Nice little backgrounder: https://siliconmasters.co/blogs/our-blog/how-photomasks-for-...