The big issue today is leakage currents. They typical account for around 30%-50% of total chip thermal budget, and they get increasingly difficult to control with smaller devices and lower voltages. They're also get worse with increased temperature(!).
The stacked devices here aren't the worst for leakage currents, but they're not fantastic either. Look at the 2nd graph in section 5: You'll see that the current never drops to zero over the range of gate-source voltages (for V_DS=0.7V). The minimum point is the best-case leakage current, and you can see it's well above zero! (The units on the vertical axis of the graph are unknown btw: The label reads as "current drain-source, arbitrary units")
Reducing trace length seems to be the way forward for faster/larger circuits. Signal propagation time on-die is becoming an issue.
Things like Huawei's Logic folding, or TSVs, and so on, attack the issue by reducing signal travel time.
This looks like another building block in that direction.
There's also some push at cooling chips from both sides.
The big barrier remains heat and this 3D stacking (aka CFET) makes heat worse by increasing density. It's possible much of the density gains offered by CFETs will remain unutilized unless other approaches to solve the fundamental heat problem are found, possibly discovering new high-conductivity MDI materials.
https://semiengineering.com/the-race-to-replace-silicon/
https://www.plantengineering.com/semiconductor-material-that...