https://www.theregister.com/systems/2026/06/29/zuck-saves-me...
From a quick skim, you could think of this as roughly equivalent to shoving a large amount of DDR4 on a PCIe card and using it as a swap space. It's more sophisticated (see CXL protocol), but that gives you an idea of the tradeoffs. It seems there is some OS-level support for moving hot/cold pages between the main fast DRAM and the expansion higher latency DRAM.
It's a very valid point that DRAM has a fairly long lifetime and contains significant embedded carbon emissions, as well as the current availability crisis of new DRAM.
I have 32GB of DDR3 that would be great for scratch space or cache of i could throw it on a card.
Hi - thanks for the insightful comment - could you please expand on the above?
Genuinely curious :)
"Second, memory dominates the carbon footprint of the fleet [8], accounting for 69% of CO2 emissions and posing a significant sustainability challenge [4]. DRAM dominates datacenter embodied CO2 largely because it is ubiquitous and deployed in large quantities across essentially all servers. Based on our internal fleet data, and aligned with studies from other hyperscalers such as Microsoft [33], memory is one of the largest single embodied-emissions contributors"
[8] U. Gupta, M. Elgamal, G. Hills, G.-Y. Wei, H.-H. S. Lee, D. Brooks, and C.-J. Wu, “ACT: Designing Sustainable Computer Systems with an Architectural Carbon Modeling Tool,” in Proceedings of the 49th Annual International Symposium on Computer Architecture (ISCA’22), 2022.
[4] D. Azevedo, M. Patterson, J. Pouchet, and R. Tipley, “Carbon usage effectiveness (cue): A green grid data center sustainability metric,” White paper, vol. 32, 2010.
[33] J. Wang, D. S. Berger, F. Kazhamiaka, C. Irvene, C. Zhang, E. Choukse, K. Frost, R. Fonseca, B. Warrier, C. Bansal, J. Stern, R. Bianchini, and A. Sriraman, “Designing Cloud Servers for Lower Carbon,” in Proceedings of the 51st Annual International Symposium on Computer Architecture, ser. ISCA ’24, 2025, p. 452–470.
Not a reference, but I found https://www.interface-eu.org/publications/semiconductor-emis... which goes into great detail on the subject. I hadn't realized there were significant emissions of fluorinated gases directly from the fabs, which is mildly alarming. Although it looks like there has been a crackdown on this either politically or through ESG policies.
Which seems to be the sister site of Register; https://www.blocksandfiles.com/architecture/2026/06/26/panmn...
I seem to remember the market for doing similar with flash got neutered over patent issues, but I can't recall the details. And flash cache did end up being a market, at least for bigger players. Maybe something similar happened here, or maybe it just hit a niche I cared about at the time?
[1] I know there were a handful of products in this space, but my impression is they never really took off. I could be wrong. [2] Definitely can in NetBSD; I've done it for archs like VMEbus where it's common to have a small, fast on board memory and much slower, often larger memory out on the bus. I assume this sort of thing is enabled in Linux by the work to support NUMA, but I've never looked into it.
I would counter tho that 1) this isn't the first time there's been a memory price/supply crunch, and "I've got a drawer full of last gen memory I can't use" is kinduva IT cliche, and 2) 'more memory' has always been a pain point, especially with industry practices like chipsets only supporting relatively small physical memory relative to address space (e.g. all those Intel LGA775 chipsets that capped at 4 or 8GB). Oh, and 2a) 'faster disk' has always been a pain point...
But, yeah...obviously my impression of things doesn't match market reality.
They seemed to stop making them altogether around when SSDs came out which probably shrunk the market niche right out of viability.
[1] https://www.amazon.com/High-Speed-Digital-Design-Handbook/dp...
Without cache coherency, you have to be more careful about how you use the memory and the performance story is complex. Ram over CXL is going to have worse perf than ram on the cpu memory controller, but there shouldn't be any big gotchas.
Reminds me of the days of JBOD arrays. Mac OS X had built-in support for it.
JBOR?
I'm not sure where 'pedantic', especially when coupled with 'contributes nothing to the discussion', wasn't worthy of a downvote (which I didn't give), but I'm sure there's a "well, ackshually..." rationale there someplace.
Edit: extra 'not' removed.
All this goes to my "world has gone insane over IP law" bucket. Similar to people disallowing their games being streamed or even shared in screenshots.
It says the source photo was uploaded as original content by a user in 2011 as a 400x300 JPEG created on an iPhone 3GS per EXIF data, with copyright released as public domain.
There’s nothing to suggest it was downscaled in the log or copyright encumbered, it just looks like it’s old/small. I often click into Wikipedia/Wikimedia Commons images where the original is available as a super high resolution option in addition to various smaller thumbnails.
It’s better for server farms where engineers can customize and tune for an architecture like this.
There have been some cards that use RAM as a storage device. They were never popular because having to set it up as a disk had very limited use cases.
"Our CXL solution achieves substantial gains for diverse workloads, including up to a 25% reduction in server count for disaggregated ML inference"
How does using worse RAM result in 25% reduction of server count for given workloads?
This yields for exciting ideas or workarounds that might result a post-crisis memory boom (hopefully) also for local machines.
1. Lowest, Apple is evaluating new Chinese manufacturer which means change of supply demand if indeed it has reasonable QA. (https://www.ft.com/content/f4ac5c92-03be-4499-b16a-017a7e9ee...)
2. Companies tries to workaround performance - suddenly single channel is 'ok' ? :) (https://www.gigabyte.com/press/news/2403)
Single channel RAM surely beats any disk-based swap.
There is a tight resource starvation/motivation loop — the demand put on RAM and SSD and GPUs by the largest frontier models is a direct motivation to make smaller LLMs. Like an evolutionary pressure making animals smaller and more food-efficient.
These smaller models, once successful, are still likely to consume more RAM and SSD and GPUs than any other application short of high quality video processing itself (the smaller LLMs and higher end video processing seem to have about the same needs). But the resources would distribute through the market more traditionally, leading to less insane cycles.
So it seems to me that the way out of the RAM/SSD price cycle crisis that manufacturers are in — where the price fluctuates between high and low due to supply constraints and then oversupply from new production capacity - is for them to fund research into smaller LLMs. They'll still sell essentially the same amount of product. Maybe more.
Weights need to be loaded into the accelerator's processor fast, which means they need to be physically adjacent to it, but there is limited physical space for that - not enough to fit the all the weights of a 1T+ param model, so weights get loaded into VRAM dynamically according to what part of the model is being run.
ROM (I guess we're talking Flash memory) can be dense, since it is built vertically - many hundreds of layers, but this comes at the cost of poor performance, so even if you could fit enough ROM next to the processor it would not be fast enough.
https://www.andysarcade.net/store2/all-other-stuff/vintage-c...
China is desperate to sell anything to... everyone. If there's a market, they'll eventually be there to fill it.
It took them decades for cars, but now they did it.
For RAM, CXMT went from 20 000 wafers per month to... 240 000 wafers per month in something like two years. And they're extending capacity massively now. It's a company only 10 years old.
The market is there and China shall flood it: that's how they operate with everything.
At some point they'll probably even come with GPUs that shall do 80% of the job for 20% of the price.
Just like you can buy chinese server motherboards at 1/5th the price of a SuperMicro one today.
So I'm not sure hardware is going to be only for big companies: China is going to put pressure on the OpenAI and Anthropic of this world locking all the RAM / SSDs / chips of this world.
I've recently gotten into fountain pens. Sure, a $7 Jinhao or $15 Hongdian pen isn't going to write quite as nice as a $200+ pen, but they're about 80% of the way there, and you can buy tons of them for the cost of a single more expensive pen. Plus, some models will accept Western nibs just fine which means you're buying a cheap barrel and assembling a much higher quality product for almost pennies on the dollar.
One would do well not to underestimate their ability to fill markets. It may take years, but it will happen.
Anyway, the point is that in the future you cannot own things. Whether that is because of the small market or because of other reasons, that does not matter.
I'm sure a chinese EV group could key in on the same pure-value market if there isn't a group already doing that. 'Golf carts for the street.'
TIL there are 2x 2.5GbE PCI-E HAT adapters for Pi 5.
How to attach RAM to the new NVLink/UALink fiber buses?
GPU transistors are smaller due to the more advanced process node (cost per transistor metrics aren't really clear, if they improve on advanced node or not, but I'd say they get cheaper as they get smaller, as technology costs are amortized).
I'm sure both RAM and logic use a process that is quite similar in both inputs and manufacturing steps. So while RAM is a commodity product, this insane price difference didn't make any sense.
So I guess when those fundamental inputs become a constraint, it would make sense for $/transistor move closer for both, which is a massive hike for RAM.
Is it built in different silicon, is it physical steps that's incompatible (ie its actually incompatible), is it different physical preparations that needs to be made (making it economically infeasible to combine)
I cannot help but wonder, even if the answer doesn't change anything in my life.
At a very abstract level, when you're manufacturing DRAM you need to manufacture a lot of circuit elements that have HIGH capacitance, since a DRAM cell is basically a capacitor and the higher its capacitance the less frequently it needs to be refreshed.
On the other hand, when manufacturing logic (CPU/GPU/ASIC) you want to minimize the capacitance of almost all circuit elements, since capacitance introduces delay and switching energy cost.
Nearly everything about the manufacturing processes for DRAM and logic is optimized around this fundamentally incompatible figure of merit.
I worked on the development of Intel's eDRAM process, which was used to integrate DRAM into the CPU/GPU die for Iris Pro embedded graphics from 2013-23. https://ieeexplore.ieee.org/document/6576667/
What's more, the configuration and flow of the machines used for each step are quite sensitive: you cannot in general just stand up another fab with the same machines, apply the same settings, and hit go on a new chip design and expect any yield: you need to dial in each step, certainly for each process, and likely for each design. This makes switching things around more difficult as well.
So, while in general a fab will have certain common features: spin coaters, photolithography machines, vapor deposition chambers, ovens, etc, the number and specification of each one will vary based on the process, and a production fab will generally not want to change their process drastically, or even to swap between different designs too often.
A Reddit user explains a bit here.
This in turn affects the electrical properties: parasitic resistance/capacitance, gate dielectric properties and so on. The dielectric in particular is critically different between DRAM and regular CMOS, because DRAM needs to minimise leakage (as that determines how long the memory lasts between refresh cycles).
Regular factories will retool somewhat between jobs. Because it is quite difficult to finetune a silicon process node, it is more common that a fab will set up for a particular node and then switch to "do not touch or change anything under any circumstances", as doing so may wreck yields.
("different substrate entirely" does exist: that's GaN, for power transistors in phone chargers, and SiC, for even higher power transistors.)
If you want to know more, the Asianometry youtube channel has some fairly good deep dives, such as [2] going through a decent bunch of the 45nm production process, or [3] doing the same for (early) DRAM.
[0]: https://www.youtube.com/watch?v=Bln-v9LmZ3E
[1]: https://i1.wp.com/semiengineering.com/wp-content/uploads/201...
You can't find an explanation why they're different for the same reason you can't find an explanation why writing poetry and riding a unicycle isn't the same process.
and cost per transistor stopped decreasing at ~20-30nm, now small nodes are targetting energy efficiency (and thus performance, since heat is the main limiter)
Supply and demand coupled with the fact that a RAM fab can't (trivially) output compute chips, and vice versa, a compute fab can't output RAM. It's two completely different supply chains.
Also you calculate in the machine cost and R&D.
RAM hiked because the demand spiked and these companies are now in power. Before apple and other companies told them the prices and had hardly any money for investment.
I remember being able to borrow a computer from somewhere when Diablo II had just come out in 2000 which had a 450Mhz Pentium III and 64 MB of RAM. 64MB of RAM was probably mid-tier at the time, i.e. very much not a given. As I recall Diablo II recommended 64MB for single player and 128MB for multiplayer (or above 4 players or something).
The computer I'm writing this on has 64 GB of RAM, 1024 times as much. By comparison I have a 20-core Intel CPU with up-to 3GHz speed or somewhere around there, even pretending each core could run at that max speed simultaneously (which they can't), that's only 133-times as much CPU power.
Maybe the NVMe read times are as/more significant than memory size increase, but the metrics on them isn't quite as front and center on PC specs as memory and CPU.
Hard drive capacity similarly impressive as RAM in terms of size (was apparently 10-30GB in 2000), but I don't have a 10TB hard disk as I don't need one that big (1TB is plenty for me), so again it's not as impactful to me as memory.
Over that time CPUs have also increase their instructions per clock by 3 to 4 times, so the comparison is a bit closer than that. 5Ghz in CPUs is also common these days which would make it even closer. RAM has also improved in more than just total size though.
This is a shockingly ill thought-out comment tbh. I don't want to assumr you're an LLM, perhaps we can blame morning grogginess.
And, yeah, the memory thing hasn't aged well. Thing is, 1984 was a funny time in computing, particularly when you consider the kind of computers normal people had access to.
At that point even things like PCs and the new Mac had 128 or 256K of RAM[0], so I get that 3MB must have seemed like an ocean of memory at the time. And, realistically, more than 1MB of RAM in machines you'd typically see sat at home or on a desktop was uncommon until the beginning of the 1990s.
And, although Moore's law had been around since 1965 it's hard to know how aware people outside of specialist circles would have been of it in 1984.
I suppose Gibson must have done some pretty in depth research for Neuromancer, right? But the memory thing is sort of ancillary to the story, so how much would he really have focussed on that? Probably not much.
And then do you really want to harshly judge the book on that one slightly laughable thing, in other ways, it was incredibly forward looking and almost prophetic? Doesn't seem right.
I think the sensible position is you have to let it slide and see it as a possible alternative future that never quite came to pass in that way but that which we can see strong echoes and foreshadowings of even still.
[0] In 1984 microcomputers, as opposed to, cough, "serious" computers like the PC and Mac, with 128K of RAM were still very new, with 32 - 64K being the entry level, and if you had one with 128K you were king of the hill. 128K in 1984 seemed like a ton of memory to most of us, but it's worth bearing in mind that only a handful of years before computers like the ZX81, which had only 1K of RAM, were the common entry level, so the progression was already clear if you looked at the situation in the right way, but you had to have been paying attention for a while to have noticed. I remember the first time I used a machine with 4MB of RAM in, maybe, 1990 - an Archimedes at school - and feeling like it was just this absolutely inexhaustible ocean of memory. In 1984 3MB would have felt almost inconceivably huge unless you were in the high performance computing, or maybe the mainframe, worlds.
Isn't he on record that his documentation was listening to techies talking shop in bars?
> And then do you really want to harshly judge the book on that one slightly laughable thing about memory when, in other ways, it was incredibly forward looking and almost prophetic.
He seems to understand humans. Gibson's world and Brunner's Stand on Zanzibar are imo the most "prophetic" sf books written so far.
Yeah. I don’t think he was a technophile himself. Which might have helped him because he was not trying to be realistic. But at the same time there are things he understood deeply.
Yeah, I think this is it. The humans were the point, not the minutiae of the tech.
(Btw, I hadn't noticed you'd responded whilst I was editing my comment to express myself a bit more clearly - I hope anyway - so the quotes don't quite match but I don't think it matters, because the sentiment is hopefully clear enough both ways!)